1. Field of the Invention
The present invention relates to a semiconductor device which operates by applying voltage to a control electrode such as an EST (Emitter Switched Thyristor) or the like.
2. Description of the Background Art
FIG. 18 is a sectional view showing a configuration of a conventional EST. As shown in FIG. 18, an N.sup.- epitaxial layer 52 is formed on a first major surface of a P.sup.+ substrate 51, a P diffusion region 53 is formed on a surface of the N.sup.- epitaxial layer 52, N.sup.+ diffusion regions 54a, 54b and 54c are selectively formed in a surface of the P diffusion region 53.
Then, a gate electrode 55a is formed through an insulating film 56 on the P diffusion region 53 between the N.sup.- epitaxial layer 52 and the N.sup.+ diffusion region 54a, while a gate electrode 55b is formed through the insulating film 56 on the P diffusion region 53 between diffusion regions 54b and 54c. The gate electrodes 55a and 55b are formed of polysilicon. A cathode electrode 57 formed of aluminum silicon is formed directly on the P diffusion region 53 which is located between the N.sup.+ diffusion regions 54a and 54b. The cathode electrode 57 is formed on the N.sup.+ diffusion regions 54a and 54b as well. An anode electrode 58 of metal is directly formed on a second major surface of the P.sup.+ substrate 51.
FIG. 19 is a model sectional view for explaining an operation of the EST shown in FIG. 18. The operation of the EST will be described with reference to FIG. 19.
When the cathode electrode 57 and the gate electrode 55 (electrodes 55a and 55b) are set at the same potential and a potential at the anode electrode 58 is raised, a depletion layer expands from a PN junction between the P diffusion region 53 and the N.sup.- epitaxial layer 52 to retain voltage.
When voltage at the gate electrode 55 is raised relative to the cathode electrode 57 in this state, surface regions 53a and 53b of the P diffusion region 53 just under the gate electrodes 55a and 55b are negatively inverted. As a result, as shown by allow with broken line, electrons flow from the N.sup.+ diffusion region 54a to the N.sup.- epitaxial layer 52 while, as shown by allow with solid line, holes are introduced from the P.sup.+ substrate 51 through the N.sup.- epitaxial layer 52 to the P diffusion region 53.
In all the holes flowing into the P diffusion region 53, part of the holes flowing into the P diffusion region 53 just below the N.sup.+ diffusion regions 54b and 54c flow in lateral directions within the P diffusion region 53 as shown by the solid line arrow and reach the cathode electrode 57. At this time, a resistance R1 which the P diffusion region 53 just below the N.sup.+ diffusion region 54c serves as causes a potential at the P diffusion region 53 just below the N.sup.+ diffusion region 54c to rise relative to the cathode electrode 57. On the other hand, the N.sup.+ diffusion region 54c is electrically connected through the N.sup.+ diffusion region 54b and the negatively inverted P diffusion region 53b to the cathode electrode 57, and therefore, potential rising at the N.sup.+ diffusion region 54c is considerable smaller compared with the cathode electrode 57.
Thus, as the holes flowing in the P diffusion regions 53 increase, a region between the N.sup.+ diffusion region 54c and the P diffusion region 53 is forwardly biased, and electrons are gradually introduced through the P diffusion region 53 into the N.sup.- epitaxial layer 52. As a result, a thyristor comprised of the N.sup.+ diffusion region 54c, P diffusion region 53, N.sup.- epitaxial layer 52 and P.sup.+ substrate 1 turns ON to perform a thyristor operation. The thyristor operation enables an ON-state resistance value to be sufficiently low under an ON state of the EST. The resistance R1 is set to a sufficiently large value so that the thyristor operation may work.
Then, when voltage at the gate electrode 55 related to the cathode electrode 57 is reduced, a state of negative inversion of the P diffusion regions 53a and 53b is extinguished, and therefore, the holes introduced into the N.sup.- epitaxial layer 52 are cancelled because of a recombination within the N.sup.- epitaxial layer 52 and an introduction into the P diffusion region 53, and the thyristor turns OFF.
Although a resistance value of a resistance R2 of the P diffusion region 53 below the N.sup.+ diffusion region 53b is set sufficiently low, potential rising because of the resistance R2 causes a region between the N.sup.+ diffusion region 54b and the P diffusion region 53 to be forwardly biased when hole current introduced into the P diffusion region 53 in ON state, and a parasitic thyristor comprised of the N.sup.+ diffusion region 54b, P diffusion region 53, N.sup.- epitaxial layer 52 and P.sup.+ substrate 51 turns ON to perform a thyristor operation. Once the parasitic thyristor starts its operation, it is in a latch-up state where the gate electrode 55 is useless to turn off current flowing between the electrodes 57 and 58.
FIG. 20 is a circuit diagram showing an equivalent circuit of the EST shown in FIGS. 18 and 19. Referring to FIG. 20, the EST circuit includes an NPN bipolar transistor T1 consisting of the N.sup.+ diffusion region 54c, P diffusion region 53 and N.sup.- epitaxial layer 52, a PNP bipolar transistor T2 consisting of the P.sup.+ substrate 51, N.sup.- epitaxial layer 52 and P diffusion region 53, and an NPN bipolar transistor T3 consisting of the N.sup.+ diffusion region 54b, P diffusion region 53 and N.sup.- epitaxial layer 52. It also includes an NMOS transistor Q1 consisting of the N.sup.+ diffusion region 54a, P diffusion region 53a, N.sup.- epitaxial layer 52 and gate electrode 55a, and an NMOS transistor Q2 consisting of the N.sup.+ diffusion region 54b, P diffusion region 53b, N.sup.+ diffusion region 54c and gate electrode 55b.
The NMOS transistors Q1 and Q2 are transistors for turning ON or OFF the EST. The transistor Q2 is connected in series to a thyristor consisting of the bipolar transistors T1 and T2, and the thyristor turns ON in accordance with turning ON of the transistor Q1. The bipolar transistor T3 is a parasitic transistor of which base and emitter are short circuited by the resistance R2 so as not to be activated, but when current flowing in the resistance R2 becomes too large, a parasitic thyristor consisting of the bipolar transistors T2 and T3 is activated and latches up.
FIG. 21 is a graph showing a flow rate of the current I flowing between the electrodes 57 and 58 (referred to as "conducting current" hereinafter) related to voltage V at the gate electrode 55 (referred to as "control voltage" hereinafter) related to the cathode electrode 57. However, the conducting current I is logarithmically indicated. As shown in FIG. 21, when the conducting current I reaches a flow rate I1, it is in a latch-up state which is uncontrollable by the control voltage V.
The conventional EST is configured as mentioned above, and it has the disadvantage that increasing the conducting current I causes latch-up and the control voltage V cannot control the conducting current I. A latch-up phenomenon gives a restriction of a maximum controllable current or a maximum flow rate of the conducting current I which can be controlled by the control voltage V.
In order to gain a larger maximum controllable current, a concentration of the P diffusion region 53 under the N.sup.+ diffusion region 54b may be increased while a resistance value of the resistance R2 may be decreased to suppress the latch-up phenomenon. However, the resistance value of the resistance R2 cannot be limitlessly decreased because, unnecessarily increasing the concentration of the P diffusion region 53 under the N.sup.+ diffusion region 54b affects threshold voltage VTH of the NMOS transistor Q2 having source and drain regions of the N.sup.+ diffusion regions 54b and 54c. Thus, there arises the problem that the maximum controllable current cannot be sufficiently increased.
Also, in order to decrease hold current IK (see FIG. 21) which is a minimum current required for retaining the thyristor operation, the P diffusion region 53 and the N.sup.+ diffusion region 54c may be formed so that the P diffusion region 53 just below the N.sup.+ diffusion region 54c may be sufficiently long in order to increase the resistance value of the resistance R1, however, in such a way, a channel width of the NMOS transistor Q2 per unit area becomes small, so that the ON-state resistance during the thyrister operation becomes large, and there is a restriction in raising a resistance value of the resistance R1. Thus, there is the problem that the hold current cannot be sufficiently decreased.